[Csnd] Hardware acceleration of Csound

As a long time lurker on this list I remember the Extended Csound project (https://web.media.mit.edu/~bv/papers/extended%20csound.pdf).

As I recall, this was a system using Digital Signal Processor (DSP) chips to hardware accelerate Csound, but I believe it never really achieved commercial success and the hardware is now probably difficult or impossible to obtain/re-create.

In the interim the electronics world has moved on from discrete DSP chips to FPGAs containing a large number of programmable logic elements, with FPGAs often containing many hundreds of DSP elements available for instantiation in a design.

Programming these chips (such as the Xilinx Zynq devices found on the Zedboard and Arty dev. boards) is much easier these days with free development software allowing both hardware development using HDL languages such as VHDL or Verilog, and increasingly these days the use of high level synthesis tools (such as Vivado/Vitis HLx) which allow the translation of C language code straight to hardware logic.

My question is, are any of the Csound community aware of any attempts to utilise the inherent parallelisation of FPGAs to accelerate the performance of Csound?

It has always seemed to me that Csound, with multiple instruments and scores running in parallel, would benefit significantly from hardware acceleration and that if we could only find a way to use the HLS tools to map the core Csound opcodes into hardware then we would manage to port the implementation to many different architectures of hardware and remove future obsolescence problems such as those experienced by Extended Csound.

Of course, I may be barking up a completely pointless tree here, just wondered what the community view was…

Ges Cook

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We’ve done stuff with GPUs



but not FPGAs (yet).


Thanks Victor,

Very interesting indeed, I’ll read the papers and take a look at the Github code.